Workshops

FLEXTILES WORKSHOP at AHS-2014

½ day Workshop Associated with AHS 2014, Leicester, 18 July 2014, 9 am – 1 pm

Title: FlexTiles: Self-Adaptive Heterogeneous Many-Core Technology Based on Flexible Tiles

Abstract: This workshop will present to AHS-2014 attendees, state-of-the-art technology related to many-core platforms and will demonstrate a design methodology for the use of heterogeneous many-core processors with self-adaptation capabilities, its virtualisation layer and its tool chain, ensuring programming efficiency and low power consumption. Demonstrations of an Open Virtual Platform simulator and an FPGA emulator will illustrate the capabilities of the FlexTiles heterogeneous many-core platform.

The presentations will be given by FlexTiles partners, as follows:

First session (9:00 AM)

1.  FlexTiles Project Overview. A Heterogeneous Many-Core Platform Based on 3D Stacked Chip Technology and Programming Solutions

      • Philippe MILLET, Coordinator (Thales), 30'

2.  3-D Stacked Chip Technology and Strategies for Optimal Usage of Through Silicon Vias (TSV)

      • Romain LEMAIRE, (CEA Leti), 25

3.   FlexTiles Simulating Environment Based on Open Virtual Platform (OVP)

      • Stephan WERNER, (KIT) 25

4.    Low-Power DSP Accelerator Embedded in a Heterogeneous Many-Core Architecture.

      • Marc MORGAN,(CSEM) 25’

Coffee Break (10:45 AM)

Second Session (11:00 AM)

5.   Dynamically Reconfigurable Embedded FPGA System

      • Antoine COURTAY, (UR1), 25’

6.   Sample Application: Optical Flow Processing:

      • Invited Speaker, 30’

7.   FPGA-Based Emulation of FlexTiles Platform

      • Fynn SCHWIEGELSHOHN, (RUB), 25’

8.   Demonstration: OVP Simulation of the FlexTiles Platform

      • Stephan WERNER (KIT), 25’

For more information on the FP7 project, see the FP7 FlexTiles Project

Abstract:

A major challenge in computing is to leverage multi-core technology to develop energy-efficient high performance systems. This is critical for embedded systems with a very limited energy budget as well as for supercomputers in terms of sustainability. Moreover the efficient programming of multi-core architectures, as we move towards many-core solutions with more than a thousand processor cores predicted by 2020, remains an unresolved issue. The FlexTiles project defines and develops an energy-efficient yet programmable heterogeneous many-core platform with self-adaptive capabilities.

The many-core is associated with an innovative virtualisation layer and a dedicated tool-flow to improve programming efficiency, reduce the impact on time to market and reduce the development cost by 20 to 50%. FlexTiles raises the accessibility of the many-core technology to industry – from small SMEs to large companies – thanks to its programming efficiency and its ability to adapt to the targeted domain using embedded reconfigurable technologies.

FlexTiles is a 3D stacked chip with a many-core layer and a reconfigurable layer. This heterogeneity brings a high level of flexibility in adapting the architecture to the targeted application domain for performance and energy efficiency.

A virtualisation layer on top of a kernel hides the heterogeneity and the complexity of the many-core platform from its programmer and fine-tunes the mapping of an application at runtime. The virtualisation layer provides self-adaptation capabilities by dynamic relocation of application tasks to software on the many-core or to hardware on the reconfigurable layer. This self-adaptation is used to optimise load balancing, power consumption, hot spots and resilience to faulty modules.

The reconfigurable technology is based on a virtual bitstream that allows dynamic relocation of accelerators just as software based on virtual binary code allows task relocation. This flexibility allows the use of fault mitigation schemes, a crucial issue for future many-cores. During the execution of the application, the runtime binding is done to match the configuration defined by the virtualisation layer. It adapts the location of the code, the storage and the communication paths on the fly.

Partners:

Thales (coordinator)

Karlsruher Institut fuer Technologie (KIT)

Palaiseau, France

Karlsruhe, Germany

Technische Universiteit Eindhoven (TUE) Eindhoven, Netherlands
CSEM Centre Suisse d’Electronique et de Microtechnique SA (CSEM) Neuchâtel, Switzerland
Commissariat à l’Energie Atomique et aux Energies alternatives (CEA) Grenoble, France
Université de Rennes 1 (UR1) Rennes, France
Sundance Multiprocessor Technology LTD (SUNDANCE) London, United Kingdom
Associated Compiler Experts B.V. (ACE) Amsterdam, Netherlands
Ruhr-University of Bochum (RUB) Bochum, Germany

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