Title: Error-Resilient Circuits and Micro-Architecture Techniques for Energy-Efficient Computing


Karthik Shivashankar, ARM University Programme, R&D


Integrated circuits in modern SoCs and microprocessors are typically operated with sufficient margins to mitigate the impact of rising uncertainties at advanced process nodes. The widening safety-margins required to ensure robust computation in the face of such uncertainties inevitably lead to conservative designs with unacceptable power and performance overheads. Recently, error-tolerant circuit techniques have received increased research focus both in academia and in industry as an effective means of achieving energy-efficient computation through the elimination of these design margins. Typically, these techniques incorporate specialized circuitry to detect occasional critical-path failure due to worst-case variations. Suitable recovery mechanisms restore correct pipeline state while ensuring forward progress.

This tutorial discusses a wide spectrum of error-tolerant approaches from industry and academia, specifically highlighting ARM research in this area. In particular, a technique called “Razor" that introduced timing-speculation in microprocessor pipelines in order to eliminate voltage and frequency guard bands is reviewed. Several academic and industrial prototypes that incorporate Razor and similar techniques are reviewed. The tutorial also describes recent work that extends timing-speculation to hardware accelerators in communications and digital signal-processing applications.


Title: The LEON Processor

Part I: Overview of Past, Current and Next-Generation LEON SoC Architectures

Part II: Introduction to the Open Source LEON/GRLIB IP Library


Jan Andersson, Aeroflex Gaisler


The LEON project was started by the European Space Agency in late 1997 to study and develop a high-performance processor to be used in European space projects. The objectives for the project were to provide an open, portable and non-proprietary processor design, capable to meet future requirements for performance, software compatibility and low system cost. Another objective was to be able to manufacture in a Single Event Upset (SEU) sensitive semiconductor process. In order to maintain correct operation in the presence of SEUs, extensive error detection and error handling functions were needed.

Traditionally, a LEON SoC design has consisted of one single processor connected to a bus with a memory controller and various peripherals and communication controllers. In recent years, a shift has been made where multi-core architectures have become available for use in the harsh space environment.

The tutorial will give an overview of the VHDL design methods developed and used for the LEON project and of how the LEON processors have evolved from single CPU systems to multi-core devices, via the GR712RC processor, and currently to the ESA quad-processor Next Generation Microprocessor (NGMP) architecture.

In parallel with the architectural advancements, the environment around the LEON processor has also changed. The tutorial will describe the current state of Aeroflex Gaisler’s GRLIB IP library that includes the latest LEON processors together with over 100 peripheral IP cores. Focus will be on the free open source version of GRLIB that is currently being used for research and education by universities around the globe.


Title: SpaceWire: Fundamentals, Applications and Future Developments


Prof. Steve Parkes, Star Dundee Ltd
Jorgen Ilstad, European Space Agency


The SpaceWire tutorial will be presented by Professor Steve Parkes from the University of Dundee, who wrote the SpaceWire standard with inputs from international engineers, and Jorgen Ilstad, an experienced SpaceWire engineer from ESA who has worked supporting several ESA missions using SpaceWire and has developed several important SpaceWire technologies.

SpaceWire is a computer network for use onboard spacecraft that connects together instruments, mass-memory, on-board processors, and the downlink telemetry system. SpaceWire is simple to implement and has some specific characteristics that help it support data-handling applications in space: high-speed, low-power, simplicity, relatively low implementation cost, and architectural flexibility making it ideal for many space missions. SpaceWire provides high-speed (2 Mbits/s to 200 Mbits/s), bi-directional, full-duplex data-links, which connect together SpaceWire enabled equipment. Data-handling networks can be built to suit particular applications using point-to-point data-links and routing switches.Since the SpaceWire standard was published in January 2003, it has been adopted by ESA, NASA, JAXA and RosCosmos and is being widely used on scientific, Earth observation, commercial and other spacecraft. High-profile missions using SpaceWire include: Gaia, ExoMars rover, Bepi-Colombo, James Webb Space Telescope, GOES-R, Lunar Reconnaissance Orbiter and Astro-H.

The SpaceWire tutorial comprises two parts: SpaceWire Fundamentals and SpaceWire Applications and Future Developments.

The SpaceWire Fundamentals tutorial provides an introduction to the way in which SpaceWire works. First the various levels of the SpaceWire standard are described including the physical, signal, character, exchange, and packet levels. SpaceWire routers and networks are then introduced and the way in which a SpaceWire network operates is explained. The operation of SpaceWire time-codes, which broadcast synchronisation signals across a SpaceWire network, is explained. The Remote Memory Access Protocol (RMAP) will also be introduced. At the end of this part of the tutorial the participant will have a good understanding of how SpaceWire works.

SpaceWire Applications and Future Developments tutorial explores how SpaceWire is being used in practice. Several space missions are taken as examples and the data-handling architecture is described. The use of point-to-point links to transfer data from a high-data rate instrument to a mass-memory system is illustrated by GAIA and Sentinel 1. The use of router technology to form SpaceWire networks is illustrated with missions like BepiColombo and MTG. A brief overview of current and future developments of SpaceWire will be presented.


Title: Radiation Effects in Space, an Introduction


Stefan K. Hoeffgen, Fraunhofer INT


This tutorial will give a general introduction to radiation effects in space from the environment to testing. It will be structured into four parts:

Part 1 gives an overview of the radiation environment in space and its sources: terrestrial, solar and galacto-cosmic.

Part 2 describes the effects of the radiation attransistor level. It will concentrate on the effects relevant to CMOS technology namely Total Ionizing Dose (TID) as well as Single Event Upsets (SEU) Single Event Functional Interrupts (SEFI) and Single Event Latchup (SEL).

Part 3 gives a short overview of some radiation hardening techniques at process level.

Part 4 is concerned with the testing of the devices for TID and SEE at different facilities (Co-60, protons, and heavy ions).

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