Keynote Speakers

Title : ESA Developments for On-board Data Systems



Philippe Armbruster,

Head of Data Systems Division
European Space Agency (ESA), Netherlands



On-board data systems and data handling electronics are in constant evolution, due to the obsolescence of components and indeed to the need of increasing their performances. They follow ground technology trends, often at a slower pace, such as the ones allowing easier and faster integration by reusing building blocks. This is well reflected by on-board platform and payload computers that become not only more compact and more powerful but also more versatile. In parallel, high speed links and on-board networks (e.g. SpaceWire, SpaceFibre, Ethernet) are now widely used. They complement or even replace more conventional command and control busses (e.g. Mil1553).

On the same line, sensor links and busses (e.g. SPI, I2C, CAN) are being adapted to space use. An other interesting evolution is related to file based mass-memories (e.g. non volatile) allowing data to be easily stored on-board and retrieved by applications through standardised services and protocols. These facilities are extended to new concepts including file based operations.

On the basis of future missions for which adaptivity is an enabling requirement, the presentation addresses ESA's approach for streamlining the development of Data Systems. Starting from reference architectures, the concept of Space Avionics Open Interface Architecture (SAVOIR) is then detailed. Then the definition of generic specifications for key units such as On-Board Computers and Remote Terminal Units are addressed together with some implementation options.

Finally, functions and features supporting an adaptive behaviour of the sub-system during definition, development and operations are presented.


Philippe Armbruster received an Engineering degree in Physics and Electronics in 1983 and then a PhD in Signal and Image Processing from the Louis Pasteur University of Strasbourg in 1987, France. After having completed the development of a very high resolution image digitising and processing system for a German company, he started working in 1989 at the technical centre of the European Space Agency, ESTEC, located in The Netherlands. He was first in charge of developing signal processing devices and electronic units for on-board satellite payload data processing applications. Being nominated head of the Data Systems division in 2003, he is responsible presently for the development of radiation hardened microprocessors, computers, mass memories and on-board electronics in general. He contributed significantly to the development of the SpaceWire standard used worldwide today to implement on-board networks. Philippe Armbruster is now focusing on space avionics based on open interfaces (SAVOIR initiative) and adaptive on-board data systems.


Title: Small Satellites – the Disruptive Use of COTS Technologies


Andy Bradford

Director of Special Programmes
Surrey Satellite Technology Ltd (SSTL)
 Guildford, UK

Andy Bardford.jpg


Modern small satellites, taking advantage of the dramatic advances in commercial ‘off-the-shelf’ (COTS) technologies developed for the industrial and consumer markets, have developed capabilities that are rivalling their conventional large satellite counterparts but at considerably lower cost and shorter timescales to launch – fundamentally changing the approach to space, enabling wider participation in space activities and applications, and stimulating new business models.


Andy Bradford started his career in the space industry as a young graduate trainee (YGT) at ESA ESTEC; during this time he played a major role in the 'TeamSat' mission, which was a small satellite designed and built mainly by students and young graduates. Following this Andy worked for Bradford Engineering in the Netherlands (the name is a pure coincidence!), working mainly on small satellite studies and also propulsion systems and components for small satellites. Andy returned to the UK in 1998 to join Space Innovations Ltd (SIL) in Newbury, as a Mechanical Systems engineer, primarily working as the mechanical and AIT lead on the Australian 'FedSat' satellite. Andy joined SSTL in 2000, following the demise of SIL.  Andy's first role in SSTL was as a project manager, initially on the FedSat project, which SSTL took on from SIL. Andy went on to manage the BILSAT project from 2001 to 2003, and then the GIOVE-A project from 2003 to early 2006. After this Andy managed the Mechanical Systems Group, until August 2007 when he joined the SSTL leadership team, initially as Director of Projects. Shortly afterwards he transferred  to the role of Director of Engineering, which he held until October 2013, at which point he took up his current role of Director of Special Programmes.

Andy has an MSc in Astronautics and Space Engineering from Cranfield University and a BSc in Design Engineering.


Title: Multi-Core Processors in Critical Applications



Avelino Martin

Head of Hardware Design Assurance
 Airbus Defence and Space - Military Aircraft
Madrid, Spain



Multi-core processors (MCPs) are now proposed for use in critical applications for their increased performance and to mitigate product obsolescence. MCPs offer adaptive systems powerful features to dynamically change behavior at run-time in response to changes in the operational environment, system configuration, resource availability or other factors, but are still looked at warily in critical domains. Fault-tolerant architectures targeted at high-reliability can be, in principle, implemented in multi-core devices making full use of redundant hardware and software. In that case, the fault tolerance or at least fail safe mechanism must be provided by an external fault detection function.

However MCPs contain built-in components that are not present in single-core processors which can provoke nondeterministic interference between the software applications executing on the separate cores. In addition, some MCPs can dynamically change the behaviour of the processors in the absence of external input upon fulfilment of certain criteria.

This presentation will discuss the reasons why we are compelled to use multi-core processors, the issues these devices pose in critical applications and possible solutions to them.


Avelino Martin is Head of the Hardware Design Assurance Department at Airbus Defence and Space Military Aircraft. He has over 25 years of electronic engineering experience including expertise in Space Hardware and Microelectronics Design. Before Airbus Defence, Avelino held a SoCCER group position at EADS ASTRIUM (SoC/IP) involving work on complex hardware certification compliance issues.

Avelino is the co-author of the CEPA 2 Micro-Electronics White Book (Military Aerospace Roadmaps, for Western European Union Ministries of Defence) on ASIC – FPGA – IP – SoC and participates in a number of Airborne Electronic Hardware certification transnational (European / American) working groups. He holds a Telecommunications Engineering Degree from the Technical University of Madrid.

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